1. Field of the Invention
This invention relates to voltage converters, especially to DC-DC or switched voltage regulators and to methods and apparatus for control of such regulators, in particular to providing current limiting control, for example for protecting from a current overload or short-to-ground situation and/or during start up.
2. Description of the Related Art
Voltage converters such as DC-DC converters are used in a range of different applications. FIG. 1 shows a typical application where processor circuitry 101, which may, for example, be a processor of a portable electronic device, is supplied with a voltage VOUT (102) by a DC-DC converter 100. The DC-DC converter 100 receives an input voltage VIN (103) and an external clock signal CLK (104) and outputs the required voltage output VOUT (102). Typically the required processor supply voltage varies with processor frequency, which can vary with processing load. When the processing load is light, the processor reduces its operating frequency and hence the required voltage in order to save power. The processor circuitry 101 therefore provides voltage select signals VSEL (105) to the DC-DC converter 100 to select an appropriate voltage output VOUT. The voltage select signals may be digital signals for controlling a programmable element of the DC-DC converter, such as a level shifter, as will be described later. The DC-DC converter 100 may also be operable in various modes, as will be described later, and the processor circuitry may select a particular mode of operation by appropriate mode control signals MODE (106). It will be appreciated that DC-DC converters may be used to provide power to device sub-systems other than processors and the embodiments described herein are generally applicable to many DC-DC converters or switched voltage regulators used for many applications.
A conventional current-mode buck (i.e. step down) DC-DC converter 200 is shown in simplified form in FIG. 2. The converter 200 comprises two nested feedback loops, an inner Current Control loop and an outer Voltage Control loop.
The Current Control loop block 201 takes an input signal VERROR and a current sense signal ISNS fed back from the output stage and generates pulse-width modulated drive signals for the output stage 202. The voltage on the output stage output node LX is switched between ground and supply, VIN, at a controlled duty cycle, resulting in a triangular current waveform in the inductor L. The inductor L and output capacitor C1 act as a filter to ensure an average voltage VOUT at an output node 203.
In operation the inductor current is sensed, and compared with VERROR. So this feedback loop generates an output sensed current varying according to the input signal VERROR. In many conventional DC-DC converters the sensed current is a peak current, although it is known to use an average current in some converters. Alternatively the minimum or “valley” current may be used to control the duty cycle of the converter.
Variation of the delivered output current, smoothed by the output filter L, C1, modulates the output voltage at VOUT. This voltage VOUT is fed back, translated down to an appropriate voltage VOUT—LS by a Level Shifter, or Voltage Shifter, block 204, to the input of a Voltage Error Amplifier block 205. The Voltage Error Amplifier block 205 compares this processed version of VOUT with a supplied reference voltage VREF and provides the error signal VERROR which drives the above described inner feedback loop to close the outer feedback loop and thus stabilize VOUT at the desired voltage.
The Level Shifter 204 is illustrated as a resistive potential divider. The level shifter applies a conversion to the level of VOUT such that, when VOUT is equal to the desired or target output voltage, the level shifted signal VOUT—LS has a known relationship to the reference voltage VREF (e.g. the level shifted signal VOUT—LS may be equal to VREF when VOUT is exactly the desired output voltage). The Level Shifter 204 may be programmable, mechanically or digitally, to provide different voltage scaling or shifting circuitry, so as to allow the converter to be configurable to output different values of VOUT. For instance, it may be programmable by a digital multi-bit signal, such as the VSEL signal generated by a processor as shown in FIG. 1.
The Voltage Error Amplifier block 205 is illustrated as including an Operational Transconductance Amplifier (OTA) 206 driving an RC network 207, but could include some other amplifier. The RC network 207, or other impedances provide closed-loop stabilization.
The Current Loop Control block 201 receives a signal 208 from the output stage 202 which passes through a Current Sensor Amp block 209 to pre-condition it, for instance to scale or strobe the signal, representative of the inductor current, to generate a convenient current sense signal ISNS. A duty modulator 210 compares the ISNS signal to the input VERROR to derive drive signals of the appropriate duty cycle to drive the output stage devices (10, 20) on and off via a Switch Driver buffer stage 211. The Duty Modulator 210 may require a clock signal 212 and a Ramp Generator 213 to generate the necessary sequence of pulses as would be understood by one skilled in the art. The ramp Generator 213 may generate a slope compensation ramp signal VISLP which may be added either in whole or in part to the ISNS signal and/or the VERROR signal so as to prevent sub-harmonic oscillations as would be well understood by one skilled in the art.
The Output Stage 202 in general will have a high-side driver device such as a PMOS transistor 10 to switch the output to the high-side supply rail 214 (VIN) and a low-side driver device such as an NMOS transistor 20 to switch the output to the low-side supply rail 215 (Ground). The Output Stage 202 is also required to supply information, i.e. an indication, of inductor current signal 208, to feed back to the Current Control block 201.
In electronic equipment in general, and particularly for fast-moving segments such as portable consumer devices (e.g. mobile phones, MP3 players etc), there is a relentless push to use the latest processor technology to increase the device capability and feature set while reducing power and cost. As the next generation of processors becomes available, lower operating voltages are used than in previous-generation processors so as to allow a reduction in process feature size, i.e. W/L, that enables a greater level of integration. This is beneficial in terms of reduced die size, reduced die cost and reduced power consumption.
These trends result in two design challenges for DC-DC converters to service these applications: one induced by the choice of the value of the low voltage; the other by battery technology lagging behind the change to lower processor supply voltages.
(i) The reduction in processor supply voltage requires a much tighter control—in absolute terms—of the DC-DC converter output voltage under prevailing processor load and battery conditions. If the control over the processor supply voltage is not sufficient, problems with under- or overvoltage may occur; both are equally undesirable.
(ii) Since the battery terminal voltage has not dropped appreciably, and the duty cycle of a DC-DC converter is given by the ratio of VOUT/VIN, duty cycles must therefore reduce. This, coupled with the desire for small external components pushes the DC-DC converter to high operating frequencies, resulting in extremely short switch on i.e. conduction, times. The increase in switching speed afforded by the reduction in transistor feature size is not normally available for the power switches since the interface components must be rated to battery voltage.
Since small conduction periods, i.e. on times, of the power switches are difficult to control, it is becoming increasingly difficult to control the lower processor output voltages with adequate accuracy using traditional Peak Current Mode control methods. Valley Current Mode (VCM) is an alternative method of control of a DC-DC converter which has been proposed. This method of DC-DC loop control controls the input transistor off, i.e. non-conduction, time, rather than the on time. For the low duty cycle required, the non-conduction time is longer than the conduction time, so is therefore easier to control. Also VCM is known to offer an inherently higher bandwidth and an improved transient response.
One known problem with DC-DC converters is voltage overshoot and large in-rush currents on start-up of the converter. This is especially an issue for Valley Current Mode converters as the high side device driver current is only indirectly controlled. A start-up mode which minimises these problems, but allows start up to the full load would be advantageous.
Another known problem with DC-DC converters is providing current limit protection for current overload situations such as protection against short-to-ground. Conventional current limiting schemes conventionally monitor the PMOS current for the purposes of current limiting and provide turn off of the PMOS when the current limit is reached. However, in a short-to-ground situation the voltage difference across the inductor can be high during the PMOS conduction period and near zero during the NMOS conduction period, with the result that the inductor current decays slowly. Even turning the PMOS on for a short period, sufficient to allow comparison to the current limit, can increase the current than more than it decays during the rest of the cycle. This results in so-called stair-stepping of the inductor current, where the inductor current is ramped up on a cycle by cycle basis.